1. Field of the Invention
The present invention relates to an image processing apparatus, and more particularly to the encryption of image data.
2. Related Background Art
FIG. 1 is a block diagram of a configuration of a prior art image encoding apparatus having an encryption function.
FIG. 2 is a block diagram of an image decoding apparatus for decoding the image data encoded by the apparatus of FIG. 1.
In the encoding apparatus shown in FIG. 1, numeral 110 denotes a high resolution analog video signal (hereinafter referred to as an HD signal), which, in the present example, has 1,050 scan lines and a frame frequency of 30 Hz. Relative to the HD signal, a video signal of an ordinary resolution having 525 scan lines, a frame frequency of 30 Hz and pixels 858 is referred to as an SD signal.
An HD A/D conversion circuit 112 samples the video signal 110 at a sampling frequency of 54.054 MHz to convert it to a digital signal. By virtue of the sampling frequency, the number of pixels per line of the digital HD signal is 1,716. A high resolution (HD)/ordinary resolution (SD) conversion circuit 114 reduces the number of pixels to one half in both the vertical direction and horizontal direction to output a video signal of the ordinary resolution having 525 scan lines, the frame frequency of 30 Hz and 858 pixels per line.
An encoding circuit 116 efficiently encodes the digital SD signal outputted from the conversion circuit 114 by an encoding scheme which is a combination of motion compensated adaptive prediction encoding and DCT. A decoding circuit 118 decodes the encoded signal outputted from the decoding circuit 116 to reproduce an SD signal. An SD/HD conversion signal 120 interpolates pixels to the output video data from the decoding circuit 118 by a factor of two in both the vertical direction and horizontal direction to convert it to an HD signal. Namely, the SD/HD conversion circuit 120 outputs a signal corresponding to the high resolution video signal having 1,050 scan lines, 1,716 pixels per line and the frame frequency of 30 Hz.
A subtractor 122 subtracts the output of the SD/HD conversion circuit 120 from the output of the A/D conversion circuit 112 for each pixel. The output of the subtractor 122 is referred to as an auxiliary video signal. An encoding circuit 124 encodes the output of the subtractor 122 in the same encoding scheme as that for the encoding circuit 116.
A multiplexing circuit 126 multiplexes the encoded data (the encoded SD signal) outputted from the encoding circuit 116 and the encoded data (the encoded auxiliary video signal) outputted from the encoding circuit 124 and outputs it to an encryption circuit 128. The encryption circuit 128 encrypts the output of the multiplexing circuit 126 in accordance with an encryption key signal of an encryption key output circuit 130, and an output unit 132 outputs the encrypted data outputted from the encryption circuit 128 to a transmission line. As described above, the transmission line may be a communication line or a recording medium.
The encryption is briefly described with reference to FIGS. 3 and 4. The following encryption techniques are available.
FIG. 3 is a flow chart of the encryption by the U.S. Data Encryption Standard (DES) published in the FIPS Publication 46 dated Jan. 15, 1977, and FIG. 4 shows a function of the encryption of FIG. 3. The data encryption algorithm of the DES is published as the "Data Encryption Standard" as described above. Referring to FIGS. 3 and 4, the DES is explained.
The DES converts block encryption to binary data comprising 0's and 1's. In the DES, the binary data is grouped into 64-bit blocks and the transposition and the replacement are repeated for each block to encrypt it. An encryption key is a 64-bit signal, of which 8 bits are check bits for detecting an error. Thus, a 56-bit encryption key is actually effective. The replacement of the digit is controlled by the encryption key in each cycle. FIG. 3 shows an encryption process of the DES. FIG. 4 shows a function fK(R) which is the heart of the encryption.
As shown in FIG. 3, a 64-bit plain text is first transpositioned. This is a fixed transposition independent from the encryption key. Then, the 64 bits are divided into a left half L.sub.0 and a right half R.sub.0. Then, the following operations are repeated over the 16 stages: EQU L.sub.n =R.sub.n-1 EQU R.sub.n =L.sub.n-1 +fk.sub.n (R.sub.n-1) (1)
where + represents a sum of mode 2 for each bit, L.sub.n and R.sub.n represent the left half 32 bits and the right half 32 bit, respectively, at the end of the operation for the n-th stage, and K.sub.n is generated from the encryption key as shown in the right side of FIG. 3. In FIG. 12, s.sub.1 . . . s.sub.16 are 1 or 2.
Condensed transposition is defined as the transposition excluding some of the input. In FIG. 3, 8 bits out of the 56 input bits are excluded so that an output comprises 48 bits. The condensed transposition is irrevocable conversion so that the input cannot be perfectly reproduced from the output. This serves to make the estimation of the encryption key difficult.
Referring to FIG. 4, the function fK(R) in FIG. 3 is specifically described. In FIG. 4, to generate the function fK(R), augmented transposition is made to R. The augmented transposition is defined as the overlapped transposition of some inputs. In the illustrated example, 16 bits out of the 32 input bits appear in overlap at the output. K composed by the key is mode 2 added to the output. The resulting 48 bits are divided into eight 6-bit blocks and the respective 6 bits are converted to 4 bits by s.sub.1, s.sub.2, . . . s.sub.8, respectively. Assuming that the 6 bits constitute one character, it may be considered as a type of replacement. However, since the output is compressed to 4 bits, the conversion is irrevocable. Accordingly, the fK(R) is generally an irrevocable function. This, however, does not mean that the conversion of the formula (1) is irrevocable. The formula (1) may be converted as follows: ##EQU1## It is thus seen that L.sub.n-1 and R.sub.n-1 can be calculated from L.sub.n and R.sub.n.
The calculation of the formula (1) is repeated 16 times and when L.sub.16 and R.sub.16 are determined, they are finally transpositioned again and the encryption is terminated.
In a decoding apparatus shown in FIG. 2, a transmission data input unit 140 receives the data from the transmission line and supplies it to a decryption circuit 142. The decryption circuit 142 decrypts it by utilizing the encryption key signal outputted from the encryption key output circuit 144. In order for the decryption to be correctly performed, the exactly same encryption key as that outputted from the encryption key output circuit 130 used in the encoding apparatus (see FIG. 1) should be used.
The decryption is substantially a reverse operation to the encryption. Briefly, the process proceeds from the bottom to the top in FIG. 3. First, a reverse transposition to the last transposition in the encryption is made, and R.sub.n-1 and L.sub.n-1 are determined from the formula (2), and when R.sub.0 and L.sub.0 are determined, a reverse transposition to the first transposition in the encryption is made. In this manner, the original 64 bits are reproduced. In order to decrypt the DES encrypted text, there is no known method other than examining the keys one by one. Assuming that one microsecond is needed to examine if one key is correct one or not, 2,283 years is needed to examine all of 2.sup.56 keys.
The transmission data decrypted by the decryption circuit 142 is separated by a separation circuit 146 to encoded data of the SD signal and encoded data of the auxiliary video signal, which are supplied to decoding circuits 148 and 150, respectively. The decoding circuit 148 outputs the reproduced SD signal and the decoding circuit 150 output the reproduced auxiliary video signal.
An SD A/D conversion circuit 152 converts the digital SD signal outputted from the decoding circuit 148 to an analog signal. The output of the SD A/D conversion circuit 152 is an analog video signal having 525 scan lines and the frame frequency of 30 Hz. This video signal is applied to a monitor device of an ordinary resolution to display the image.
An SD/HD conversion circuit 154 converts the digital SD signal outputted from the decoding circuit 148 to a digital HD signal in the same process as that of the SD/HD conversion circuit 120. An adder 156 adds the output of the decoding circuit 150 and the output of the SD/HD conversion circuit 154. The output of the adder 156 is a video signal corresponding to the high resolution video signal. An HD D/A conversion circuit 158 converts the digital output of the adder 156 to an analog signal. The output of the HD D/A converter 158 is a video signal having 1,050 scan lines and the frame frequency of 30 Hz. The video signal is applied to a high resolution monitor to display the image.
The above prior art video signal encoding and decoding apparatus has a problem in that the video signal cannot be reproduced for those who do not have the encryption key, for both the low resolution video signal and the high resolution video signal.
There is a demand that charges to users are discriminated between the low resolution display device having 525 scan lines and the high resolution display device having 1,050 scan lines, for the same content, but the prior art apparatus does not meet the requirement.